1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device and a memory system using the same which can reduce a delay time difference between output data bits during a read operation and between input data bits during a write operation.
2. Description of the Related Art
A typical memory system includes a semiconductor memory device and a memory controller. In general, a delay time difference occurs between data bits outputted from a semiconductor memory device during a read operation and between data bits inputted to the semiconductor memory device during a write operation.
The typical memory system may adjust a delay time of an input data strobe signal inputted from the semiconductor memory device together with the input data to find the optimum spacing (timing) between the input data bits, and may adjust a delay time of an output data strobe signal outputted from the semiconductor memory device together with the output data to find optimum spacing (timing) between the output data bits.
However, as the operational speed of memory systems has increased, adjusting the delay time of the input data strobe signal and the output data strobe signal has become less effective. Furthermore, since the input data bits and the output data bits which have a delay time difference are generally 1 or 2 bits, it is not efficient to arrange the delay for each input data bit and each output data bit.